1. Field of the Invention
The present invention relates generally to supporting Error Correcting Code (ECC) enabled memory devices, specifically, a novel mechanism for a Power Loss Recovery (PLR) algorithm and flash media format for flash media management software.
2. Description of the Related Art
The demand for quicker and more powerful communication devices has led to many technological advances, including flash memory and the ability to store and retain data despite the loss of power. A non-volatile memory has the ability to retain the data despite loss of power and is one of the enabling technologies for the wireless and cellular revolution.
A flash media is a system with various configurations of flash memory devices to create a non-volatile storage. One example is a system with a 32 bit bus and multiple 8 bit flash memory devices coupled to the 32 bit bus. Also, flash media could be hardware with additional decoding logic to manage and coordinate the various arrays of flash memory devices. Thus, the flash media exhibits the same flash memory device read, program, and erase characteristics. A flash media could be coupled to a file system, which has the interface and logic to manage files and directories. Thus, the interface with the file system allows for the ability to create, delete, move, read, write, and flush files and create, get, delete, read, flush, and write directories.
Typically, a flash media management software divides a flash memory block into individual data units or sectors, wherein each sector has an associated header for identifying a sector's status. Likewise, status bits or paired bits in Multi-Level Cell (MLC) flash are utilized for tracking the current state of each sector. However, as depicted in FIG. 1, the prior art flash media format interleaves the PLR status tracking information with the data units. However, an ECC enabled flash memory device might have an entire block of data unprotected by the ECC. Typically, ECC is similar to parity because additional bits of information are added to data for detecting and correcting individual bit errors. For example, a single bit error may result in a complete inverse of the ECC parity. Typically, the data may be changed to correct the single bit error. However, for an ECC enabled flash memory device that stores the ECC information, one needs to invalidate the ECC because of the single bit error. Based on FIG. 2, this may result in data that is unprotected because of the interleaving of PLR status bits with the data.